The present invention relates to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device having plural diffusion layers different in impurity concentration, wherein selected ones of the plural diffusion layers are formed with silicide layers as well as a method of forming the same.
As shrinkage of the semiconductor devices have been on the progressed, it has been required to form sallow diffusion layers. Making the diffusion layers shallower increases the resistance of the diffusion layer, thereby making it difficult for the semiconductor device to exhibit high speed performances In order to reduce the resistance of the diffusion layer, it is effective to form the silicide layer on the diffusion layer This technique for forming the silicide layer on the diffusion layer has been applied to a solid state image pick tip device having plural diffusion layers different in impurity concentration The solid state image pick up device has a photo-receiving region having diffusion layers of relatively low impurity concentrations, and a charge transfer region having a MOS transistor having source and drain diffusion layers of high impurity concentration.
FIGS. 1A through 1G are fragmentary cross sectional elevation views illustrative of conventional solid state image pick up devices having diffusion layers, parts of which are formed with silicide layers.
With reference to FIG. 1A, field oxide films 302 are selectively formed on a passive region of a p-type silicon substrate 301 by a local oxidation of silicon method, whereby an active region or a device region is defined by the field oxide films 302. A gate oxide film 303 is formed on the device region or the active region of the p-type silicon substrate 301 by a thermal oxidation of silicon. A polysilicon film is entirely formed by a chemical vapor deposition method. A phosphorus is doped into the polysilicon film to reduce a resistance of the polysilicon film. The polysilicon film is then patterned o form polysilicon gate electrodes 304. A photo-resist film is selectively formed for carrying out an ion-implantation of an n-type impurity into a shallow region of the photo-receiving region of the p-type silicon substrate 301 by use of the photo-resist as a mask at a low impurity concentration thereby to form an nxe2x88x92-type diffusion region 305 on the photo-receiving region of the p-type silicon substrate 301. The used photo-resist film is removed. In place, another photo-resist film is selectively formed. The other photo-resist film is used as a mask for carrying out another ion-implantation of an n-type impurity into a shallow region of the charge transfer region of the p-type silicon substrate 301 at a high impurity concentration thereby to form n+-type source and drain diffusion regions 306 on the charge transfer region of the p-type silicon substrate 301. The other photo-resist is then removed.
With reference to FTG. 1B, a silicon oxide film 307 having a thickness of about 25 nanometers is entirely formed which extends over the field oxide films 302, the n+-type source and drain diffusion regions 306, the nxe2x88x92-type diffusion region 305, and the polysilicon gate electrodes 304.
With reference to FIG. 1C, an ion-implantation of an n-type impurity of arsenic is carried out at a dose of about 1E14 /cm2 to introduce the arsenic through the silicon oxide film 307 into upper regions of the polysilicon gate electrodes 304, the nxe2x88x92-type diffusion region 305, and the n+-type source and drain diffusion regions 306 for snaking the above upper regions amorphous, whereby amorphous silicon layers 310 are selectively formed in the upper regions of the polysilicon gate electrodes 304, the nxe2x88x92-type diffusion region 305, and the n+-type source and drain diffusion regions 306.
With reference to FIG. 1D, a silicon oxide film 309 having a thickness of about 50 nanometers is entirely formed on the silicon oxide film 307.
With reference to FIG. 1E, a photo-resist film 308 is selectively formed over the photo-receiving region so that the photo-resist film 308 covers the nxe2x88x92-type diffusion region 305 and the field oxide films 302. The laminations of the silicon oxide films 307 and 309 are selectively removed by use of the photo-resist film 309 as a mask so as to remove the laminations of the silicon oxide films 307 and 309 from the charge transfer region.
With reference to FIG. 1F, the photo-resist film 308 is removed. A titanium film 311 is entirely deposited by a stuttering method, so that the titanium film 311 extends over the field oxide film 302, the amorphous silicon regions 310 over the n+-type source and drain diffusion regions 306, and the other amorphous silicon regions 310 over the polysilicon gate electrodes 304 as well as over the remaining part of the silicon oxide film 309.
With reference to FIG. 1G, a heat treatment, for example, an anncal is carried out at a temperature in the range of 600-900xc2x0 C. to cause a silicidation reaction of silicon in the amorphous silicon regions 310 with titanium of the titanium film 311, whereby titanium silicide layers 312 having a thickness of about 30 nanometers are selectively formed over the n+-type source and drain diffusion regions 306, and over the polysilicon gate electrode 304 in the charge transfer region, whilst the unreacted titanium film remains 311 over the field oxide film 302 and over the silicon oxide film 309. The unreacted titanium film 311 is then removed by a mixture of ammonia solution with hydrogen peroxide solution. As a result, the polycide gate is formed in the charge transfer region. Since the silicidation reaction is caused between the titanium film with the amorphous silicon regions 310, then the titanium silicide layers 312 are thick and have a reduced resistance.
Although illustration is omitted, an inter-layer insulator is entirely formed over the charge transfer region and the photo-receiving region. Contact holes are selectively formed in the inter-layer insulator, so that the contact holes reach the titanium silicide layers 312 over the n+-type source and drain diffusion regions 306. Contact plugs are selectively formed in the contact holes and an aluminum interconnection layer is formed over the inter-layer insulator so that the aluminum interconnection layer is connected through the contact plugs to the titanium silicide layers 312 over the n+-type source and drain diffusion regions 306.
As described above, in order to form the amorphous silicon regions, an ion-implantation of arsenic into all of the diffusion layers is carried out at a relatively high dose, for example, about 1E14 /cm2. Namely, arsenic is ion-implanted into not only the n+-type source and drain diffusion regions 306 but also the nxe2x88x92-type diffusion region 305 having the low impurity concentration in the photo-receiving region, whereby the surface region of the nxe2x88x92-type diffusion region 305 is increased and made much higher than 1E14 /cm2. It is, therefore, impossible to form the diffusion layer having the lower impurity concentration than about 1E14 /cm2.
In order to avoid the above problem, it is required to selectively make the diffusion layers amorphous. In Japanese laid-open patent publication No. 11-40679, it is disclosed that amorphous silicon layers are selectively formed over diffusion layers in a first region and no amorphous silicon layers are formed in a second region, before first silicide layers are formed on first interfaces between the amorphous silicon regions and the titanium layer, whilst second silicide layers are formed on second interfaces between the silicon regions and the titanium layer, wherein the first silicide layers are thicker than the second silicide layers. This conventional technique is to form concurrently silicide layers different in thickness from each other. The conventional technique is never to form selectively the silicide layers over the diffusion layers of the high impurity concentration but no silicide layers over the diffusion layers of the low impurity concentration. The conventional technique is never settle the above problems to be solved by the present invention.
In the above circumstances, it had been required to develop a novel semiconductor device and method of forming the same free from the above problem.
Accordingly, it is an object of the present invention to provide a novel semiconductor device free from the above problems.
It is a further object of the present invention to provide a novel semiconductor device having at least a first diffusion layer having a first impurity concentration and at least a second diffusion layer having a second impurity concentration lower than the first impurity concentration, wherein a silicide layer is formed over the first diffusion layer whilst no silicide layer is formed over the second diffusion layer.
It is a still further object of the present invention to provide a novel method of forming a semiconductor device free from the above problems.
It is yet a further object of the present invention to provide a novel method of forming a semiconductor device having at least a first diffusion layer having a first impurity concentration and at least a second diffusion layer having a second impurity concentration lower than the first impurity concentration, wherein a silicide layer is formed over the first diffusion layer whilst no silicide layer is formed over the second diffusion layer.
The first present invention provides a semiconductor device having; at least a first diffusion layer having a first impurity concentration; at least a second diffusion layer having a first impurity concentration which is lower than the first impurity concentration, and the first and second diffusion layers being of the same conductivity type, wherein a silicide layer is formed over the first diffusion layer, whilst no silicide layer is formed over the second diffusion layer.
The second present invention provides a method of selectively forming a silicide layer in a semiconductor device having a first impurity concentration; at least a second diffusion layer having a first impurity concentration which is lower than the first impurity concentration, and the first and second diffusion layers being of the same conductivity type. The comprises the steps of: forming a mask layer at least over the second diffusion layer; carrying out a first ion-implantation of an impurity of the same conductivity type as the first and second diffusion layers by use of the mask layer as a mask so as to ion-implant the impurity into an upper region of the first diffusion layer, whereby an amorphous silicon layer is formed over the first diffusion layer whilst no amorphous silicon layer is formed over the second diffusion layer; forming a metal layer on the amorphous silicon layer over the first diffusion layer and also on the mask layer; and carrying out a heat treatment to cause a silicidation reaction of metal in the metal layers with silicon in the amorphous silicon layer whereby a metal silicide layer is selectively formed over the first diffusion layer whilst no silicide layer is formed over the second diffusion layer.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.